Failed to halt RISC-V core

When trying to debug an embedded application on the DE2-115 board again, I got this issue:

 Error: Fatal: Hart 0 failed to halt during examine()

What was the issue? Has anyone seen this?


Please review document Common issues and Solutions (Version 1.0 22/8/22) point 1.5

Extract of this document :

Explanation: The RISC-V core for the previous debug session was not cleaned up.
Solution: Reset RISC-V core by pressing reset button on the FPGA board. On DE2-115, it’s
button KEY0